PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
PIPE SerDes Architecture for PCIe Gen 5 and Beyond - Verification - Cadence Blogs - Cadence Community
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
MindShare - PIPE 6.0 - PHY Interface for PCI Express and more
Demystifying PIPE interface packets using the in-built descrambler module in UltraScale+ Devices Integrated Block for PCI Express Gen3
PCI Express PIPE interface functional coverage – VerifSudha
PIPE 5.0: 34% signal count reduction for PCI Express 5.0 – VerifSudha
PCIe Hard IP for Intel® Arria® 10 and Intel® Cyclone® 10
PCI Express 3.0, 2.0, 1.1 Controller IP Core - Configurable
PCS Pipe IP Core IP Core
PCIe 5.0 Controller | Interface IP - Rambus
PCI Express PIPE interface functional coverage – VerifSudha
PCIe/USB/SATA PHY Application Example | Renesas
Products | PLDA is now a part of Rambus.
PCIe 6.0 Controller | Interface IP - Rambus
Rambus Delivers PCIe 6.0 Controller for Next-Generation Data Centers
PIPE SerDes Architecture for PCIe Gen 5 and Beyond - Verification - Cadence Blogs - Cadence Community
Atria Logic
PIPE SerDes Architecture for PCIe Gen 5 and Beyond - Verification - Cadence Blogs - Cadence Community
Overcoming SoC design challenges moving to PCIe Gen3 - Embedded Computing Design
PCIe Gen4 Standards Margin-Assisted Outer-Layer Equalization for Cross-Lane Optimization in a 16GT/s PCIe Link | 2018-11-09 | Signal Integrity Journal
The Advantages of the PCIe SerDes Architecture and its Functionality
PLDA PCIe 3.1 Controller | Interface IP - Rambus
